The testing of a logic circuit generally includes two related tests: a functional test and a fault test. The functional test involves the application of various test patterns to the primary inputs of the circuit and a monitoring of the output signals. The output signals are compared to expected values to verify logic levels and timing The fault test determines whether the circuit contains fabrication errors. The fault test is usually designed to detect as many faults as possible in a particular "fault model". Often, the "single stuck-at" fault model is used, where each fault corresponds to an input or output of a logic gate or other element in the circuit becoming fixed at a particular logic state.
As the functional test and fault test are related, they are sometimes combined If there is a fault in the circuit, it is possible that it will show up during the functional test. "Fault coverage" is a phrase which is commonly used to express how many or what percentage of potential faults in a given fault model would be detected during a test. As the complexity of circuits increases there is often a decrease in the fault coverage of the functional test. The reason that fault coverage is less than 100% is that many potential fault sites in a complex circuit are relatively inaccessible. In other words, a long sequence of test patterns may be required to propagate or reveal the fault at a primary circuit output. As the number of inaccessible fault sites increases, the time required to develop test patterns and to test the circuit becomes excessive.
Another approach to fault testing is the use of a scan path. A scan path is a serial connection of various sequential elements (flip-flops, latches, etc.) in the circuit The scan path normally has its own input and output pins The scan path elements are modified during the circuit design so that logical values (scan patterns) may be serially shifted into and out of the elements This allows the elements to be preloaded with selected logic values and their contents to be removed and examined during testing
If a scan path connects all of the sequential elements in a circuit it is referred to as "full scan." Full scan provides good fault coverage but requires a correspondingly high amount of chip space to accommodate the scan path. If the scan path connects only some of the sequential elements in the circuit it is referred to as "partial scan." Partial scan requires less chip space but obviously allows direct access to fewer sequential elements.
Critical issues for the testing of logic circuits are the design of test patterns for the functional test and the design of the scan path and scan patterns. Typically, the circuit designer first develops test patterns for functional testing The test patterns and circuit design are then provided to an automatic fault simulator. The fault simulator determines which faults in the fault model are not detected by the functional test. The fault simulator achieves this by simulating each fault while applying the test patterns Faults which are not detected are identified in a list of undetected faults.
In order to obtain greater fault coverage, a fault test is often used in addition to the functional test. This test can be written by the circuit designer, a test expert, or can be generated by an automatic test pattern generator. The test pattern generator, a software program, automatically generates sequences of additional test patterns to reduce the number of undetected faults. The problem with this approach is that the automatically generated test patterns sequences are frequently long and often only detect a single fault. To reach a desired level of fault coverage, an excessive number of test patterns may be required. An additional problem with automatic test pattern generators is that they may require the circuit designer to have extensive knowledge of their operation. Finally, even when operated by a knowledgeable user, the test pattern generator may not be capable of achieving the desired fault coverage in a reasonable amount of time.
If a scan path is to be employed, some automatic test pattern generators also provide guidance on which sequential elements in the circuit to combine in a scan path. For both partial and full scan paths, such test pattern generators provide test patterns and patterns for the scan path. However, even with the use of scan paths, test pattern generation often results in long sequences of test patterns which can greatly increase the testing time for a circuit.